1. Field of the Invention
The present invention relates to current mirror circuits. More particularly, the present invention relates to a low-voltage current mirror having reduced mirroring error.
2. The State of the Art
The basic prior-art current mirror, shown in FIG. 1, is well known. Current source 10 is coupled to the drain and gate of n-channel MOS transistor 12 and to the gate of n-channel MOS transistor 14.
The basic principle of operation of the current mirror of FIG. 1 is that if the VGS voltages of two identical MOS transistors 12 and 14 operating in the saturation region are equal, then their channel currents should be equal and in first approximation expressed as follows:Ii=I0=(β/2)(W/L)(VGS−Vth)2
There are three effects that cause the current mirror to operate differently from the ideal case: channel length modulation; threshold offset between two different transistors; and imperfect geometrical matching. The second and third effects result from process and layout imperfections.
The first effect, known as the Early effect, depends on the shortening of the effective channel length in the saturation region caused by Vds being greater than Vdsat limit (Vdsat=Vgs−Vth). Under these conditions, the depletion region around the drain junction becomes increasingly wider, causing the standard drift transport equations to be substituted by more complex equations which take into account the diffusion effect of charge through the depleted region due to the negative concentration gradient.
This effect becomes more evident as the channel length L decreases. The Early effect coefficient λ is inversely proportional to L(λ∝1/L). The following expression of an NMOS drain current in the saturated region translates the preceding considerations, giving an idea of how the real mirrored current will differ from the reference current.Ii=I0=(β/2)(W/L)(VGS−Vth)2(1+λVds)
Considering the small-signal equivalent circuit, it is possible to derive the output resistance, which is a good measure of the perfection of a current mirror as a current source. Higher performance current mirrors will attempt to increase the value of rout with respect to the standard case.
The standard current mirror of FIG. 1 has no limitation on Vin min and Vout min, that is Vimin≈Vth1; Vomin≈Vdsat2 
The current mirror of FIG. 1 suffers from the Early effect if Vds≠Vgs. It has a low output impedance ro=1/go:ro=1/λIo in the saturation region.
Referring now to FIG. 2, a prior-art Wilson current mirror is shown. This current mirror introduces a negative feedback loop with the addition of n-channel MOS transistor 16. If Io increases, the current Ii mirrored by n-channel MOS transistor 14 tries to increase in contrast to the hypothesis that Ii is constant. Vi decreases in order to counter this effect, thus reducing the current flowing through n-channel MOS transistor 14. This effect can also be explained in terms of output impedance increase induced by negative current feedback. As the n-channel MOS cascode transistor 14 enters the linear region, the output impedance of this current mirror decreases, countering the advantageous effects of the feedback structure.
In order to make the Wilson current mirror more symmetrical, a NMOS diode formed from n-channel MOS transistor 18 may be added to its first branch as shown in FIG. 3, thus equalizing the Vds voltage drop across n-channel MOS transistor 12 and n-channel MOS transistor 14. This results in an output impedance equal to that of the current mirror of FIG. 2, but the mirroring factor (ε=Io/Ii) has been improved.
Referring now to FIG. 4, a prior-art cascode current mirror is shown. This cascode current mirror is similar to the Wilson mirror, but the gates of n-channel MOS transistor 12 and n-channel MOS transistor 14 are coupled to the drain of n-channel MOS transistor 12 instead of to the drain of n-channel MOS transistor 14.
Like the Wilson current mirror, the cascode current mirror of FIG. 4 has a high output impedance and mirroring precision, since these improvements are dependant on the saturation of the n-channel MOS transistor 18. However, like the Wilson current mirror, the cascode current mirror is penalized by the minimum Vi and/or Vo operating value, which is about 2Vth.
Referring now to FIG. 5, a prior-art high-swing cascode current mirror is shown. This circuit introduces a n-channel MOS source-follower transistor 20 between the gates of n-channel MOS transistor 18 and n-channel MOS transistor 16 and n-channel MOS bias transistor 22 in series with n-channel MOS source-follower transistor 20. N-channel MOS source-follower transistor 20 acts as a level shifter, thus biasing n-channel MOS transistor 14 at the high limit of its saturation region. Like the cascode current mirror of FIG. 4, the high-swing cascode current mirror of FIG. 5 has a high output impedance but has the advantage of reducing the minimum Vo operating value. The Vi is subject to the same limitation as the cascode current mirror of FIG. 4.
All of the current mirrors of FIGS. 1 through 5 are limited in their minimum power supply voltage value VDD. This limiting factor makes these circuits unsuitable for low-voltage applications.
Referring now to FIG. 6, a current mirror is shown in which a biasing circuit including n-channel MOS transistor 24 driven from current source 26 has been added to drive the gates of n-channel MOS transistors 16 and 18. N-channel MOS transistor 12 is not in diode configuration, having its gate coupled to the drain of n-channel MOS transistor 18.
If the transistors in the circuit are properly sized ((W/L)18=(W/L)16=(m/n)2(W/L) and (W/L)0=(1/(1+n/m)2(W/L)) it is possible to reduce the minimum Vi and V0 operating value to about only one Vth (if m>>n) without affecting the large output impedance and to improve the current matching capability (being Vds1=Vds2+(Vdsat)W/L), thus improving the mirroring factor ε=I0/Ii.